1. Field of the Invention
The invention relates generally to a flash memory cell and method of manufacturing the same. More particularly, the invention relates to a flash memory cell and method of manufacturing the same, which can prevent a moat generated when a self-aligned floating gate of a flash memory cell is formed and can improve the coupling ratio between the floating gate and a control gate.
2. Description of the Prior Art
In general, a flash memory cell is implemented by a shallow trench isolation (STI) process using a device isolation process. When the isolation process of a floating gate using mask patterning is performed, wafer uniformity is very bad depending on variations in the critical dimension (CD). It is thus difficult to implement a uniform floating gate. Further, there is a problem of programming and erasure fail in the memory cell depending on variations in the coupling ratio. Also, the mask process is made further difficult in implementing a small spacer of below 0.15 μm in view of a higher-integrated design. As a result, a process of manufacturing the flash memory cell being an important factor in implementing the uniform floating gate is made further difficult.
Due to the above problems, if the floating gate is not uniformly formed, the memory cell is over erased when the memory cell is programmed and erased since the difference in the coupling ratio is large. As a result, there are problems that the operating speed of the device is lowered and the operation of the device at a low voltage is made impossible. Due to addition of the mask process, there are problems that the yield of the product is lowered and the cost of the product is increased. Further, there is a problem of a fail in the device, etc. due to a moat (i.e., a shape in which an active region of the field oxide film is concaved by a subsequent etch process) that generates in the STI process or nitride-spacer local oxidation of silicon (NS-LOCOS) process. It is therefore necessary to increase the coupling ratio by securing a cell in which the moat is not generated in a flash device of a high-integration level.